Time and location:
October 24, at 13:00-17:00
University of Oslo, Ole-Johan Dahls Hus, Gaustadalleén 23 B, room 5462 “Informatikksalen”.
Nordic Semiconductor is a leader in the field of low-power ASIC design in particular for Bluetooth solutions. The ASIC design industry has gone through many transformations but low-power has always been a design goal. Since the emergence of Internet-of-Things in recent years, low-power design has begun to receive far more focus than ever before. In the start of this tutorial, we’ll focus on the process and the unique challenges in designing increasingly complex circuits in the domain of low-power integrated circuits. We’ll talk about the design cycle starting from front-end RTL entry all the way to back-end and further into the post-production.
In the second part of the tutorial, we will cover design of an IP that is independent of a general-purpose processor’s supervision. Implementation of such IPs will enable peripheral to peripheral communication over a system-on-chip while processor’s sleep can be maximized thereby saving a lot of power dissipation. A complex SoC can have different power domains running at different frequencies to optimize energy consumption but exchange of data between these domains are prone to synchronization problems popularly known as Clock Domain Crossing (CDC) issues. This tutorial will also discuss CDC issues and their solution. The IPs over an SoC can be exchanging large streams of data over a congestion-prone AXI network and techniques to resolve such situations are important part of SoC design and will be highlighted in this tutorial.
Waqar Hussain, Nordic Semiconductor, Norway
Omer Qadir, Nordic Semiconductor, Norway
Berend Dekens, Nordic Semiconductor, Norway
There is a separate fee for the tutorial attendance: 120 / 100 EUR.