Reconfigurable Architectures and Network-on-Chips for Massively Parallel Signal Processing

Special Session on Reconfigurable Architectures and Network-on-Chips for Massively Parallel Signal Processing


  • Waqar Hussain, Nordic Semiconductor, Norway
  • Omer Qadir, Nordic Semiconductor, Norway
  • Berend Dekens, Nordic Semiconductor, Norway
  • Anja Dekens, Nordic Semiconductor, Norway
  • Saeeid Oskuii, Nordic Semiconductor, Norway

Abstract and topics

The performance requirements of emerging wireless standards are increasingly intensive for signal processing specially in the domain of Internet-of-Things (IoT). Traditional architectures do not typically provide hardware features to meet the ever-growing performance requirements. Adding support for computational reconfigurability and dynamic routing to a modern system-on-chip can have wide-ranging benefits – from high throughput to flexibility and fast turnaround time for upcoming wireless standards. The tradeoff is additional power and area cost which can be kept at minimum if the reconfigurability is tailored to the application domain. The custom design and reconfiguration features of such platforms can save power and energy dissipation to unprecedented levels. Such reconfigurability can be provided at compute units as well as at the interconnect levels of a system-on-chip.

The researchers in both academia and industry deal with a series of challenges. A strong demand for high-performance, low-power, and easy maintainability of systems has been the main drivers when selecting a computing platform for signal processing. We are therefore inviting participants to submit papers on their latest achievements and contributions in any of the topics mentioned below:

  1. Architecture, design, and implementation strategies for reconfigurable multicore systems.
  2. Multi-metric performance analysis of reconfigurable architectures and Network-on-Chips.
  3. Programming models in heterogeneous multicore/manycore systems.
  4. Reconfiguration in multicore/manycore systems.
  5. FPGA- and CGRA-based multicores.
  6. Issues related to Dark Silicon.
  7. Network-on-Chip Infrastructures supporting multicore platforms.
  8. IoT baseband protocol (or other key application signal processing) implementation on heterogeneous multicores.
  9. Standalone applications vs. operating systems driven approach in multicore architectures.
  10. Compilation and simulation tools, models, etc. for the programming, testing and validation of complex architectures.
  11. Design-space exploration case-studies and tools.
  12. Survey articles, e.g., market trends in heterogeneous architectures for product development.


See the submission page to see how to submit a paper to this session. Special Session papers will undergo similar reviews as any other papers submitted to the conference.