Tutorials

There will be two tutorials at 13-17 on Monday October 19, 2026:

Tutorial A: Low energy deep learning using software-only approach

Instructor: Luigi Carro, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

Abstract: Currently, deep learning is a key technology for the development of new applications and services. One of the critical aspects to DL adoption is the high operational cost of foundational ML algorithms, like LLMs, CNNs, and forest-trees. This cost arises from the large volume of data and the extensive computational infrastructure required to run these algorithms. In this context, this tutorial aims to explain the main energy dissipation sources of ML algorithms, and to show software strategies that can drastically reduce the energy consumption of key ML algorithms, by exploring opportunities throughout the execution chain. The strategies presented in this tutorial are based on real-life examples, and enable programmers to achieve huge energy reductions, achieving this by only software modifications.

Program::

Introduction to the problem: the importance of low energy in the software domain, and the carbon footprint of software systems
Review of basics architecture and organization in CPUs and GPUs; sources of energy dissipation in processor based systems.
Basic data structures and their energy consumption; exploiting locality to reduce energy in classical algorithms.
Real life example from CNNs, forest-trees, LLMs and SLMs
A discussion on open research problems in the topic.

Bio: Luigi Carro holds a degree in Electrical Engineering from the Federal University of Rio Grande do Sul (1985), a master’s degree in Computer Science from the Federal University of Rio Grande do Sul (1989) and a doctorate in Computer Science from the Federal University of Rio Grande do Sul (1996). He is currently a professor at the Institute of Informatics at the Federal University of Rio Grande do Sul. He has experience in the area of Computer Engineering, with an emphasis on Hardware and Software for Embedded Systems, working mainly on the following topics: low energy systems, processor architecture dedicated hardware and software accelerators, fault-tolerant circuits, embedded systems testing and software development for multi-platforms.

Tutorial B: Embedding Intelligence at the Sensor Nodes: Moving Beyond Edge AI with Hardware-Native Learning Systems

Instructors: Sayani Majumdar and Kapil Bhardwaj, Tampere University, Finland

Abstract: Our news feeds today are filled with exciting innovations that promise to make yet another aspect of our life easier. Many of these innovations belong to the class of autonomous systems such as drones, robots, self-driving cars, and intelligent monitoring platforms that is finding applications in smart homes, industrial automation, security and health sectors. These systems have greatly benefited from modern Edge AI solutions. However, in the excitement around AI algorithms, we pay less attention to the need for efficient hardware that can run these computationally heavy algorithms reliably, quickly, and at a sustainable power budget.

Modern autonomous systems are driven by complex sensor-fusion pipelines supported by high-end processors, GPUs, or even cloud servers. Although proved reliable, this architecture creates major hardware challenges, including high energy consumption, latency, excessive data movement, heat generation, and reduced component lifetime. Notably, adding the much-needed fault-tolerance, that is needed to maintain system performance under harsh environmental conditions, further increases the computational load due to additional software layers. As a result, even simple but urgent decisions, such as generating a warning or triggering a safety response, may require an unnecessarily heavy processing pipeline. In this tutorial, we will address how intelligence can be embedded in hardware directly, may it be at the sensor nodes, sensor-fusion stage, or at the memory and logic layer, removing the reliance upon main processor and cloud connectivity. We will discuss local components and hardware networks that can process sensor information near its source to trigger faster and low-power decisions. Emerging capacitive memories are promising for this purpose because their internal physics allows us to enable brain-inspired learning with ultra-low power requirements. These non-volatile synaptic memory elements, when supported by compact analog circuitry, can enable local learning, reliable decision-making ensured by the inherent fault tolerance. This approach can be called hardware-native learning where learning emerges from memory device physics and the peripheral hardware, not from any software algorithms or neural-network support. Finally, we will focus on our recently demonstrated associative learning approach as a potential hardware-learning mechanism, and our future work that aims to make these systems more reliable, practical, and suitable for real-time autonomous applications.

Biographies:

Sayani Majumdar: Dr. Sayani Majumdar is an Associate Professor of Electrical Engineering at the Faculty of Information Technologies and Communication Sciences at Tampere University, Finland. She is also a visiting professor at the Miin Wu School of Computing at National Cheng Kung University, Taiwan. Her career in semiconductor device research spans more than two decades where she worked in both academia and in close collaboration with the industry. She worked on several emerging technologies in world-leading organizations including MIT, USA and Max-Planck Institute, Germany. Her team’s current research focuses on the development of embedded non-volatile memories and neuromorphic computing hardware using low-thermal budget ferroelectric and semiconductor materials and processes for their back-end-of-line integration with CMOS circuits for their application in low-power neuromorphic edge devices. She leads multiple national, European and international projects on emerging memories and Neuromorphic computing and work as Managing Committee member in European COST Action network on Neuromorphic Computing.

Kapil Bhardwaj is a postdoctoral fellow at the CMOS and Beyond: Devices and Systems Research Group. His current research focuses on developing low-power neuromorphic circuits for multimodal sensor fusion, aiming to make decision-making efficient in autonomous systems. By leveraging the inherent physics of emerging memory devices, he aims to design energy-efficient and compact hardware solutions that can operate reliably under harsh environmental conditions. Alongside this, he has gained substantial experience in SPICE modeling of solid-state devices, peripheral circuits of in-memory computing systems, and various kinds of CMOS-based analog and mixed-signal circuits. This multidisciplinary expertise supports his broader vision of integrating novel memory and computing paradigms into next-generation intelligent systems. He has authored and co-authored more than 40 research articles in peer-reviewed international journals and conference proceedings and collaborated with experts from various globally reputed research institutions.