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IEEE Nordic Circuits and Systems Conference

Keynotes

Keynote Speakers

Davide Rossi

Davide Rossi, University of Bologna, Italy

RISC-V Inside: A Decade of PULP Chips

Abstract

Open-source hardware has evolved from early experimental efforts such as OpenRISC and OpenCores into a powerful approach for designing increasingly complex chips. The emergence of the RISC-V instruction set architecture accelerated this transformation, enabling a global ecosystem of open and extensible processor and system IPs. Within this context, the PULP (Parallel Ultra-Low Power) platform has played a key role in advancing energy-efficient and heterogeneous computing through numerous real silicon implementations. This keynote will present the PULP perspective on the evolution of RISC-V, showcasing real chips that demonstrate how open IPs can enable innovative architectures, from ultra-low-power processors to highly parallel and heterogeneous systems. Finally, it will discuss how increasingly complex systems-on-chip, heterogeneous accelerators, and advanced integration technologies are pushing open hardware toward new levels of performance, energy efficiency, and scalability.

Bio

Davide Rossi received the PhD degree from the University of Bologna, Italy, in 2012, where he currently holds the position of Associate Professor. He is the Director of the Digital Design and Open Hardware Research Line at Chips-IT. His research focuses on energy-efficient digital architectures and silicon implementations for heterogeneous and reconfigurable multi- and many-core systems-on-chip. This includes architectures, design and implementation strategies, and runtime support aimed at addressing performance, energy efficiency, and reliability challenges in both high-end embedded systems and ultra-low-power computing platforms, including aspects related to heterogeneous integration. In these research areas, he has authored more than 100 papers published in international peer-reviewed conferences and journals.

 

Sara Vinco

Sara Vinco, Politecnico di Torino, Italy

Seeing the Whole System: A Cross-Domain Perspective on Electronic Design

Abstract

Electronic systems bring together circuits, computing architectures, software, power sources, and physical processes. Each part can be modeled and optimized in detail, but the behaviour of the complete system often depends on how these parts interact. A design choice that improves one metric may change energy consumption, timing, temperature, or reliability elsewhere. How can we see those consequences early enough to make informed decisions?
This keynote explores that question through examples from virtual prototyping and multidisciplinary simulation. It shows how functional and extra-functional properties can be examined together, and why integrating models of circuits, software, physical components, and their environment introduces new challenges. Differences in abstraction, timing, and simulation semantics matter: the models must interact meaningfully while preserving the insights each specialized view provides.
As electronic systems become more heterogeneous, reasoning across domain boundaries becomes essential to understanding how a design will behave in practice. Following the consequences of design choices through the system can reveal trade-offs and potential failure modes earlier in the design process.

Bio

Sara Vinco has been an Associate Professor in the Department of Control and Computer Engineering at Politecnico di Torino since 2021. Her research focuses on the modeling, simulation, and design of electronic and cyber-physical systems, with particular attention to the interactions among functional behavior, energy, timing, temperature, and reliability. Her work also spans virtual prototyping, digital twins, and data-driven approaches for industrial applications. She is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and of Design Automation for Embedded Systems. She serves on the Executive Committee of DATE and was Program Chair of ICCD 2024. She has authored more than 100 peer-reviewed publications, and is an IEEE Senior Member and a member of IFIP Working Group 10.5.

 

Abu Sebastian

Abu Sebastian, IBM Research, Switzerland

In-Memory Computing for AI acceleration: An Overview and Future Prospects

Abstract

Analog in-memory computing (AIMC), in which synaptic weights are stored in nanoscale nonvolatile memory devices and computations are performed in the analog or mixed-signal domain, offers a compelling brain-inspired path toward the next generation of deep-learning accelerators. In the first part of this presentation, I will review recent progress in AIMC, with a focus on a 64-core chip fabricated in 14 nm CMOS technology and integrating phase-change memory. The chip achieves classification accuracy comparable to floating-point implementations while demonstrating the seamless integration of analog computing cores with digital processing units. This work establishes a foundation for heterogeneous mixed-signal computing architectures. I will also present recent demonstrations spanning a range of applications, highlighting the chip’s versatility and value as a research platform. In the second part of the talk, I will discuss ongoing efforts to develop the next generation of AIMC chips for deep-learning inference, including architectures designed to support neural-network models with billions of parameters.

Bio

Abu Sebastian is a Distinguished Research Scientist at IBM Research – Zurich, where he leads the AI Compute Frontiers group in Rüschlikon, Switzerland. He is also affiliated with the Kirchhoff-Institut für Physik at Universität Heidelberg. For his contributions to micro- and nanoscale mechatronic systems, he was honored with the IEEE Control Systems Technology Award in 2009 and the IFAC Mechatronic Systems Young Researcher Award in 2013. His research in exploratory memory technologies and emerging computing paradigms has also earned him three prestigious European Research Council (ERC) grants: the Consolidator Grant (2015), the Proof-of-Concept Grant (2020), and the Advanced Grant (2025). At IBM, he was recognized as a Master Inventor and appointed Principal Research Scientist in 2018, later becoming a Distinguished Research Scientist in 2020. In 2019, he received the Ovshinsky Lectureship Award for his contributions to phase-change materials for cognitive computing. Prof. Sebastian has served on the technical program committees of leading conferences including IEDM, AICAS, NVMTS, and E\PCOS, and has been an editor or guest editor for journals such as Mechatronics, APL Materials, Applied Physics Letters, and IEEE Design & Test. He is a Fellow of the IEEE.

 

Olli Närhi

Olli Närhi, Nordic Semiconductor, Finland

The V-model as the backbone of AI-driven chip design
Abstract
AI coding agents can now generate RTL, firmware and testbenches in hours. The bottleneck is knowing what is correct, and cheap implementation is making the V-model practical at last: one set of requirements and an executable system model drive every design level in parallel. This keynote offers a view on what this takes in practice, and where analog, RF and silicon still set the limits.
Bio
Olli Närhi is R&D Director of the Long Range Business Unit at Nordic Semiconductor in Finland, responsible for the development of cellular IoT, DECT NR+ and satellite connectivity products. He graduated from Tampere University of Technology in 1995, started his career as an analog designer, and has since led chip projects ranging from RFICs to multi-RAT SoCs. He uses AI agents daily in his own work and is leading his unit’s move to AI-first engineering.