Keynotes

Abstract

Analog in-memory computing (AIMC), in which synaptic weights are stored in nanoscale nonvolatile memory devices and computations are performed in the analog or mixed-signal domain, offers a compelling brain-inspired path toward the next generation of deep-learning accelerators. In the first part of this presentation, I will review recent progress in AIMC, with a focus on a 64-core chip fabricated in 14 nm CMOS technology and integrating phase-change memory. The chip achieves classification accuracy comparable to floating-point implementations while demonstrating the seamless integration of analog computing cores with digital processing units. This work establishes a foundation for heterogeneous mixed-signal computing architectures. I will also present recent demonstrations spanning a range of applications, highlighting the chip’s versatility and value as a research platform. In the second part of the talk, I will discuss ongoing efforts to develop the next generation of AIMC chips for deep-learning inference, including architectures designed to support neural-network models with billions of parameters.

Bio

Abu Sebastian is a Distinguished Research Scientist at IBM Research – Zurich, where he leads the AI Compute Frontiers group in Rüschlikon, Switzerland. He is also affiliated with the Kirchhoff-Institut für Physik at Universität Heidelberg. For his contributions to micro- and nanoscale mechatronic systems, he was honored with the IEEE Control Systems Technology Award in 2009 and the IFAC Mechatronic Systems Young Researcher Award in 2013. His research in exploratory memory technologies and emerging computing paradigms has also earned him three prestigious European Research Council (ERC) grants: the Consolidator Grant (2015), the Proof-of-Concept Grant (2020), and the Advanced Grant (2025). At IBM, he was recognized as a Master Inventor and appointed Principal Research Scientist in 2018, later becoming a Distinguished Research Scientist in 2020. In 2019, he received the Ovshinsky Lectureship Award for his contributions to phase-change materials for cognitive computing. Prof. Sebastian has served on the technical program committees of leading conferences including IEDM, AICAS, NVMTS, and E\PCOS, and has been an editor or guest editor for journals such as Mechatronics, APL Materials, Applied Physics Letters, and IEEE Design & Test. He is a Fellow of the IEEE.

Abstract

Open-source hardware has evolved from early experimental efforts such as OpenRISC and OpenCores into a powerful approach for designing increasingly complex chips. The emergence of the RISC-V instruction set architecture accelerated this transformation, enabling a global ecosystem of open and extensible processor and system IPs. Within this context, the PULP (Parallel Ultra-Low Power) platform has played a key role in advancing energy-efficient and heterogeneous computing through numerous real silicon implementations. This keynote will present the PULP perspective on the evolution of RISC-V, showcasing real chips that demonstrate how open IPs can enable innovative architectures, from ultra-low-power processors to highly parallel and heterogeneous systems. Finally, it will discuss how increasingly complex systems-on-chip, heterogeneous accelerators, and advanced integration technologies are pushing open hardware toward new levels of performance, energy efficiency, and scalability.

Bio

Davide Rossi received the PhD degree from the University of Bologna, Italy, in 2012, where he currently holds the position of Associate Professor. He is the Director of the Digital Design and Open Hardware Research Line at Chips-IT. His research focuses on energy-efficient digital architectures and silicon implementations for heterogeneous and reconfigurable multi- and many-core systems-on-chip. This includes architectures, design and implementation strategies, and runtime support aimed at addressing performance, energy efficiency, and reliability challenges in both high-end embedded systems and ultra-low-power computing platforms, including aspects related to heterogeneous integration. In these research areas, he has authored more than 100 papers published in international peer-reviewed conferences and journals.